41 STK12C68-IM pin names a 0 - a 12 address inputs w write enable dq 0 - dq 7 data in/out e chip enable g output enable v ccx power (+5v) v ss ground v cap capacitor hsb hardware store/busy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v a a a a a a a a dq dq dq dq dq dq dq dq v v w hsb a a a g a e ss 7 6 5 4 3 2 1 0 0 1 2 8 9 10 7 6 5 4 3 cap a 12 11 ccx a a a a a a a a a a a a dq dq dq dq dq dq dq g a e dq vss v w hsb 7 12 6 5 4 3 2 1 0 0 1 8 9 11 10 7 6 2 3 4 5 top view 4 5 6 7 8 9 10 11 12 32 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 v cap ccx 28 - lcc 28 - 300 cdip pin configurations a a a a a a 4 5 6 7 8 eeprom array 256 x 256 store recall static ram array 256 x 256 row decoder store/ recall control aaaaa 0 1210 12 dq dq dq dq dq dq dq dq 0 1 2 3 4 5 6 7 g e w column i/o column decoder input buffers aa 011 a 3 a 9 12 hsb logic block diagram STK12C68-IM cmos nvsram 8k x 8 autostore? nonvolatile static ram industrial temperature/military screen features ? industrial temperature with military screening ? 25, 35 and 45ns access times ? 15 ma i cc at 200ns access speed ? automatic store to eeprom on power down ? hardware or software initiated store to eeprom ? automatic store timing ? 100,000 store cycles to eeprom ? 10 year data retention in eeprom ? automatic recall on power up ? software initiated recall from eeprom ? unlimited recall cycles from eeprom ? single 5v 10% operation ? commercial and industrial temperatures ? available in multiple standard packages description the simtek STK12C68-IM is a fast static ram (25, 35 and 45ns), with a nonvolatile eeprom element incor- porated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resides in eeprom . data transfers from the sram to the eeprom ( the store operation ) take place automatically upon power down using charge stored in an external 100 m f capacitor. transfers from the eeprom to the sram (the recall operation) take place automatically on power up. soft- ware sequences may also be used to initiate both store and recall operations. a store can also be initiated via a single pin. the STK12C68-IM is available in the following packages: a 28-pin 300 mil ceramic dip and a 28-pad lcc. mil-std-883 and standard military drawing (smd 5962-94599) devices are also available.
42 STK12C68-IM note b: i cc and i cc are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. note c: bringing e 3 v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. see mode selection table. note d: v cc reference levels throughout this datasheet refer to v ccx if that is where the power supply connection is made, or v cap if v ccx is connected to ground. dc characteristics (v cc = 5.0v 10%) d i cc b average v cc current 95 ma t avav = 25ns 85 ma t avav = 35ns 80 ma t avav = 45ns i cc average v cc current during store 7 ma all inputs 0.2v or 3 (v cc - 0.2v) i cc b average v cc current 15 ma e 0.2v, w 3 (v cc C 0.2v) at t avav = 200ns others 0.2v or 3 (v cc C 0.2v) i cc average v cc current during autostore? cycle 4 ma all inputs 0.2v or 3 (v cc - 0.2v) i sb c average v cc current 39 ma t avav = 25ns (standby, cycling ttl input levels) 35 ma t avav = 35ns 32 ma t avav = 45ns e 3 v ih ; all others cycling i sb c average v cc current 3 ma e 3 (v cc C 0.2v) (standby, stable cmos input levels) all others v in 0.2v or 3 (v cc C 0.2v) i ilk input leakage current (any input) 1 m av cc = max v in = v ss to v cc i olk off state output leakage current 5 m av cc = max v out = v ss to v cc v ih input logic "1" voltage 2.2 v cc +.5 v all inputs v il input logic "0" voltage v ss C.5 0.8 v all inputs v oh output logic "1" voltage 2.4 v i out = C4ma except hsb v ol output logic "0" voltage 0.4 v i out = 8ma except hsb t a operating temperature -40 85 c 1 2 3 4 1 2 3 absolute maximum ratings a voltage on typical input relative to v ss . . . . . . . . . . . . . C0.6v to 7.0v voltage on dq 0-7 and g. . . . . . . . . . . . . . . . . . .C0.5v to (v cc +0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . . . C55 c to 125 c storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . C65 c to 150 c power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1w dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15ma note a: stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. (one output at a time, one second duration) industrial symbol parameter units notes min max note e: these parameters are guaranteed but not tested. symbol parameter max units conditions c in input capacitance 8 pf d v = 0 to 3v c out output capacitance 7 pf d v = 0 to 3v capacitance e (t a =25 c, f=1.0mhz) input pulse levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss to 3v input rise and fall times. . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels. . . . . . . . . . . . . . 1.5v output load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 ac test conditions 5.0v output 480 ohms 30pf including scope and fixture 255 ohms figure 1: ac output loading 1 3
43 STK12C68-IM no. parameter units note c: bringing e 3 v ih will not produce standby currents until any nonvolatile cycle in progress has timed out. see mode selection table. note e: parameter guaranteed but not tested. note f: for read cycle #1 and #2, w is high for entire cycle. note g: device is continuously selected with e low and g low. note h: measured 200mv from steady state output voltage. read cycle #1 f,g dq (data out) address data valid 2 t avav 3 t avqv 5 t axqx read cycles #1 & #2 sram memory operation address e g dq (data out) data valid 2 t avav 1 t elqv 6 t elqx 4 t glqv 8 t glqx 10 t elicch 11 t ehiccl 7 t ehqz 9 t ghqz i cc active standby read cycle #2 f 1t elqv t acs chip enable access time 25 35 45 ns 2t avav t rc read cycle time 25 35 45 ns 3t avqv g t aa address access time 25 35 45 ns 4t glqv t oe output enable to data valid 10 20 25 ns 5t axqx t oh output hold after address change 5 5 5 ns 6t elqx t lz chip enable to output active 5 5 5 ns 7t ehqz h t hz chip disable to output inactive 10 17 20 ns 8t glqx t olz output enable to output active 0 0 0 ns 9t ghqz h t ohz output disable to output inactive 10 17 20 ns 10 t elicch e t pa chip enable to power active 0 0 0 ns 11 t ehiccl c,e t ps chip disable to power standby 25 35 45 ns #1, #2 alt. min max min max min max symbols stk12c68-25-im stk12c68-35-im stk12c68-45-im (v cc = 5.0v 10%) d
44 STK12C68-IM no. parameter units write cycles #1 & #2 write cycle #1: w controlled i write cycle #2: e controlled i note h: measured 200mv from steady state output voltage. note i: e or w must be 3 v ih during address transitions. note j: if w is low when e goes low, the outputs remain in the high impedance state. 12 t avav t avav t wc write cycle time 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 20 30 35 ns 14 t elwh t eleh t cw chip enable to end of write 20 30 35 ns 15 t dvwh t dveh t dw data set-up to end of write 10 18 20 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 30 35 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz h,j t wz write enable to output disable 10 17 20 ns 21 t whqx t ow output active after end of write 5 5 5 ns symbols stk12c68-25-im stk12c68-35-im stk12c68-45-im previous data address e w data in data out data valid high impedance 12 t avav 14 t elwh 19 t whax 17 t avwh 18 t avwl 13 t wlwh 15 t dvwh 16 t whdx 20 t wlqz 21 t whqx address e w data in data out high impedance data valid 12 t avav 18 t avel 14 t eleh 19 t ehax 17 t aveh 13 t wleh 15 t dveh 16 t ehdx (v cc = 5.0v 10%) d #1 #2 alt. min max min max min max
45 STK12C68-IM note e: these parameters guaranteed but not tested. note n: hsb is an i/o that has a weak internal pullup; it is basically an open drain output. it is meant to allow up to 32 stk 12c68-ims to be ganged together for simultaneous storing. do not use hsb to pullup any external circuitry other than other stk12c68 hsb pins. note o: a recall cycle is initiated automatically at power up when v cc exceeds v switch . t restore is measured from the point at which v cc exceeds 4.5v. mode selection h x h x not selected output high z standby l h h x read sram output data active l l l h x write sram input data active l h h 0000 read sram output data active k,l 1555 read sram output data k,l 0aaa read sram output data k,l 1fff read sram output data k,l 10f0 read sram output data k,l 0f0f nonvolatile store output high z k l h h 0000 read sram output data active k,l 1555 read sram output data k,l 0aaa read sram output data k,l 1fff read sram output data k,l 10f0 read sram output data k,l 0f0e nonvolatile recall output high z k xxl x store /inhibit output high z i cc2 /standby m nonvolatile memory operation e w hsb a 12 - a 0 (hex) mode i/o power notes note k: the six consecutive addresses must be in order listed - (0000, 1555, 0aaa, 1fff, 10f0, 0f0f) for a store cycle or (0000, 1555, 0aaa, 1fff, 10f0, 0f0e) for a recall cycle . w must be high during all six consecutive cycles. see store cycle and recall cycle tables and diagrams for further details. note l: i/o state assumes that g v il . activation of nonvolatile cycles does not depend on the state of g. note m: hsb initiated store operation actually occurs only if a write has been done since last store operation. after the store (if any) completes, the part will go into standby mode inhibiting all operation until hsb rises. hardware store / recall symbols no. parameter min max units notes 22 t recall recall cycle duration 20 m s note o 23 t store t hlhh store cycle duration 10 ms v cc 3 4.5v 24 t delay t hlqz hsb low to inhibit on 1 m s 25 t recover t hhqx hsb high to inhibit off 700 ns note e 26 t assert t hlhx external store pulse width 250 ns note e v switch low voltage trigger level 4.0 4.5 v i hsb_ol hsb output low current 3 ma hsb = v ol , note e, n i hsb_oh hsb output high current 5 60 m a hsb = v il , note e, n hardware store / recall hsb w recall store sram inhibit software store hsb initiated store power down store brown out recall power up recall v switch v cap 24 t delay 26 t assert 22 t recall 24 t delay 25 t recover 23 t store 23 t store 23 t store
46 STK12C68-IM note p: once the software store or recall cycle is initiated, it completes automatically, ignoring all inputs. note q: noise on the e pin may trigger multiple read cycles from the same address and abort the address sequence. note r: if the chip enable pulse width is less than t elqv (see read cycle #2) but greater than or equal to t elehn , then the data may not be valid at the end of the low pulse, however the store or recall will still be initiated. note s: w must be high when e is low during the address sequence in order to initiate a nonvolatile cycle. g may be either high or low throughout. addresses #1 through #6 are found in the mode selection table. address #6 determines whether the STK12C68-IM performs a store or recall . note t: e must be used to clock in the address sequence for the software store and recall cycles. software store/recall cycle q,r,t address e dq(data out) valid address #6 address #1 valid high impedance 28 t avav 28 t avav 30 t aveln 31 t elehn 32 t ehaxn 23 t store 22 t recall 29 t elqz address #2 std. alt. min max min max min max no. parameter units symbols stk12c68-25-im stk12c68-35-im stk12c68-45-im 27 t avav t rc store/recall initiation cycle time 25 35 45 ns 28 t elqz p chip enable to output inactive 650 650 650 ns 29 t aveln t ae address set-up to chip enable 0 0 0 ns 30 t elehn p,q t ep chip enable pulse width 20 25 35 ns 31 t ehaxn t ea chip disable to address change 0 0 0 ns 32 t restore power-up recall duration 550 550 550 m s software store/recall cycle (v cc = 5.0v 10%) d
47 STK12C68-IM address locations. by relying on read cycles only, the STK12C68-IM implements nonvolatile operation while remaining compatible with standard 8kx8 srams. during the store cycle, an erase of the previous nonvolatile data is first performed, followed by a pro- gram of the nonvolatile elements. the program opera- tion copies the sram data into the nonvolatile ele- ments. once a store cycle is initiated, further input and output are disabled until the cycle is completed. because a sequence of addresses is used for store initiation, it is critical that no other read or write ac- cesses intervene in the sequence or the sequence will be aborted. to initiate the store cycle the following read se- quence must be performed: 1. read address 0000 (hex) valid read 2. read address 1555 (hex) valid read 3. read address 0aaa (hex) valid read 4. read address 1fff (hex) valid read 5. read address 10f0 (hex) valid read 6. read address 0f0f (hex) initiate store cycle once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software recall a recall cycle of the eeprom data into the sram is initiated with a sequence of read operations in a manner similar to the store initiation. to initiate the recall cycle the following sequence of read opera- tions must be performed: 1. read address 0000(hex) valid read 2. read address 1555 (hex) valid read 3. read address 0aaa (hex) valid read 4. read address 1fff (hex) valid read 5. read address 10f0 (hex) valid read 6. read address 0f0e (hex) initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvolatile information is transferred into the sram cells. the recall operation in no way alters the data in the device operation the STK12C68-IM has two separate modes of opera- tion: sram mode and nonvolatile mode. in sram mode, the memory operates as a standard fast static ram . in nonvolatile mode, data is transferred from sram to eeprom (the store operation) or from eeprom to sram (the recall operation). in this mode sram functions are disabled. store cycles may be initiated under user control via a software sequence or hsb assertion and are also automatically initiated when the power supply voltage level of the chip falls below v switch . recall opera- tions are automatically initiated upon power-up and whenever the power supply voltage level rises above v switch . recall cycles may also be initiated by a software sequence. sram read the STK12C68-IM performs a read cycle whenever e and g are low and hsb and w are high . the address specified on pins a 0-12 determines which of the 8192 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv . if the read is initiated by e or g, the outputs will be valid at t elqv or at t glqv , whichever is later. the data outputs will repeatedly respond to address changes within the t avqv access time without the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high or w or hsb is brought low . sram write a write cycle is performed whenever e and w are low and hsb is high . the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w go high at the end of the cycle. the data on pins dq 0-7 will be written into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low , internal circuitry will turn off the output buffers t wlqz after w goes low . software store the STK12C68-IM software store cycle is initiated by executing sequential read cycles from six specific
48 STK12C68-IM may optionally be pulled to v ccx via an external resistor with a value such that the combined load of the resistor and all parallel chip connections does not exceed i hsb_ol at v ol . do not connect this or any other pull-up to the v cap node. if hsb is to be connected to external circuits other than other STK12C68-IMs, an external pull-up resistor should be used. during any store operation, regardless of how it was initiated, the STK12C68-IM will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of a store operation, the part will be disabled until hsb actually goes high . automatic store operation during normal operation, the STK12C68-IM will draw current from v ccx to charge up a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. after power up, when the voltage on the v cap pin drops below v switch , the part will automatically disconnect the v cap pin from v ccx and initiate a store operation. figure 1 shows the proper connection of capacitors for automatic store operation. the charge storage capaci- tor should have a capacity of at least 100 m f ( 20%) at 6v. each STK12C68-IM must have its own 100 m f capacitor. each STK12C68-IM must have a high quality, high frequency bypass capacitor of 0.1 m f connected between v cap and v ss , using leads and traces that are as short as possible. if the autostore ? function is not required, then v cap should be tied directly to the power supply and v ccx should be tied to ground. in this mode, store opera- tions may be triggered through software control or the hsb pin. in either event, v cap (pin 1) must always have a proper bypass capacitor connected to it. in order to prevent unneeded store operations, auto- matic stores as well as those initiated by externally driving hsb low will be ignored unless at least one write operation has taken place since the most recent store cycle. note that if hsb is driven low via external circuitry and no write s have taken place, the part will still be disabled until hsb is allowed to return high . software initiated store cycles are performed regard- less of whether or not a write operation has taken place. eeprom cells. the nonvolatile data can be recalled an unlimited number of times. automatic recall during power-up, or after any low power condition (v cap < v switch ), when v cap exceeds the sense voltage of v switch , a recall cycle will automatically be initiated. if the STK12C68-IM is in a write state at the end of power-up recall , the sram data will be corrupted. to help avoid this situation, a 10k ohm resistor should be connected between w and system v cc . hardware protect the STK12C68-IM offers hardware protection against inadvertent store operation during low voltage conditions. when v cap < v switch, all externally initiated store operations will be inhibited. hsb operation the hardware store busy pin (hsb) is an open drain circuit acting as both input and output to perform two different functions. when driven low by the internal chip circuitry it indicates that a store operation (initi- ated via any means) is in progress within the chip. when driven low by external circuitry for longer than t assert , the chip will conditionally initiate a store operation after t delay . read and write operations that are in progress when hsb is driven low (either by internal or external cir- cuitry) will be allowed to complete before the store operation is performed, in the following manner. after hsb goes low, the part will continue normal sram operations for t delay . during t delay , a transition on any address or control signal will terminate sram operation and cause the store to commence. note that if an sram write is attempted after hsb has been forced low, the write will not occur and the store operation will begin immediately. hardware-store-busy (hsb) is a high speed, low drive capability bi-directional control line. in order to allow a bank of STK12C68-IMs to perform synchro- nized store functions, the hsb pin from a number of chips may be connected together. each chip contains a small internal current source to pull hsb high when it is not being driven low. to decrease the sensitivity of this signal to noise generated on the pc board, it
49 STK12C68-IM the cycle time used in figure 2 corresponds to the length of time from the later of the last address transi- tion or e going low to the earlier of e going high or the next address transition. w is assumed to be high , while the state of g does not matter. additional current is consumed when the address lines change state while e is asserted. the cycle time used in figure 3 corresponds to the length of time from the later of w or e going low to the earlier of w or e going high . the overall average current drawn by the part depends on the following items: 1) cmos or ttl input levels; 2) the time during which the chip is disabled (e high ); 3) the cycle time for accesses (e low ); 4) the ratio of reads to writes; 5) the operating temperature; 6) the v cc level; and 7) output load. preventing automatic stores the autostore ?function can be disabled on the fly by holding hsb high with a driver capable of sourcing 15ma at a voh of at least 2.2v as it will have to overpower the internal pull-down device that drives hsb low for 20 m s at the onset of an autostore ?. when the STK12C68-IM is connected for autostore ?operation (system v cc connected to v ccx and a 100uf capacitor on v cap ) and v cc crosses v switch on the way down, the STK12C68-IM will attempt to pull hsb low; if hsb doesn't actually get below v il , the part will stop trying to pull hsb low and abort the autostore ?attempt. low average active power the STK12C68-IM has been designed to draw signifi- cantly less power when e is low (chip enabled) but the access cycle time is longer than 55ns. figure 2 below shows the relationship between i cc and access times for read cycles. all remaining inputs are assumed to cycle, and current consumption is given for all inputs at cmos or ttl levels. figure 3 shows the same relation- ship for write cycles. when e is high , the chip consumes only standby currents, and these plots do not apply. 100 80 60 40 20 50 100 150 200 average active current (ma) 0 ttl cmos cycle time (ns) 100 80 60 40 20 50 100 150 200 average active current (ma) 0 ttl cmos cycle time (ns) 1 28 26 v v hsb cap ccx v ss 14 0.1uf bypass 100uf ?20% + power supply 10k ohms (optional) nvsram note: typical at 25 c figure 3 i cc (max) writes figure 2 i cc (max) reads figure 1 schematic diagram
50 STK12C68-IM stk12c68 - c 35 im ordering information temperature range im = industrial (-40 to +85 c) with military screening access time 25 = 25ns 35 = 35ns 45 = 45ns package c = ceramic 28 pin 300 mil dip with gold lead finish k = ceramic 28 pin 300 mil dip with solder dip l = ceramic 28 pin lcc
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